USB2.0 specifications time constrain inquiry

["rania_ah" <rania_ah@xxxxxxxxxxxxxxxxxxxxx>]

Dear sir,
I'm developing a USB2.0 solution on FPGA, and I'm now coding the SIE part, 
but I've a problem in the time constrain {T WTREV} as it's required to be 
from 3.0 to 3.125 msec, and it should be  > 3.0 msec , and must not exceed 
3.125, as my PHY is 60 MHZ , and it can be only guranteed with 10% , so to 
make sure that the first part of the condition realized then the counter 
should be based on the worset case (66 MHZ --> counter_limit=198,000 or more)
And to conform to the second part of the condition(3.125msec), then we must 
design the counter_limit value based on the 54MHZ clock, which leads to the 
condition of (counter_limit = 168,750 or less) ???!!!! 
So,what can I do ?????!!!!!!! ..... PLEASE HELP
Please reply as soon as you can.
   Thank you and best regards
Eng. Rania Ahmed Ali El-Morsy
Senior design engineer @ Wissam electronics Industries
Co. Tel : +2 02 3475820  -  +2 02 3475610
Fax no. : +2 02 3477210
Mobile  : 012 5026520


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