Re: IRQs and memory consistency

[Wink Saville <wink@xxxxxxxxxxx>]

Do you have a read barrier in the IRQ?

See "SMP BARRIER PAIRING" in:

http://www.kernel.org/doc/Documentation/memory-barriers.txt

-- Wink

On Wed, Apr 11, 2012 at 4:59 AM, Christopher Harvey <chris@xxxxxxxxxxxxxxxx> wrote:

On 10.04.2012 19:58, Wink Saville wrote:
> Sounds to me like there needs to be a flush of the processor cache
> by using memory barriers.

I used a wmb(); right after I set the value I wanted.

> I'm guessing that the IRQ is taken on a different thread and possibly
> a different processor and the value needs to be flushed. You might
> try having devid be an atomic_t and then use atomic_set
> and atomic_read so that the "proper" memory barriers are used.

should I use atomic ops instead of a wmb?
The interrupt can't happen until the value is assigned completely in
one thread. I'm sure.

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