Re: [PATCH] MIPS: Add support for the MIPS32 4Kc family I/D caches.
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On Tue, 22 May 2012, Ralf Baechle wrote: > > diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c > > index 18546fa..bca1447 100644 > > --- a/arch/mips/mm/c-r4k.c > > +++ b/arch/mips/mm/c-r4k.c > > @@ -1000,7 +1000,7 @@ static void __cpuinit probe_pcache(void) > > c->icache.linesz = 2 << lsize; > > else > > c->icache.linesz = lsize; > > - c->icache.sets = 64 << ((config1 >> 22) & 7); > > + c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); > > c->icache.ways = 1 + ((config1 >> 16) & 7); > > > > icache_size = c->icache.sets * > > @@ -1020,7 +1020,7 @@ static void __cpuinit probe_pcache(void) > > c->dcache.linesz = 2 << lsize; > > else > > c->dcache.linesz= lsize; > > - c->dcache.sets = 64 << ((config1 >> 13) & 7); > > + c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); > > c->dcache.ways = 1 + ((config1 >> 7) & 7); > > > > dcache_size = c->dcache.sets * > > Good catch. I'm amazed how long we were able to get away with this bug. It was not a bug, or at least not an active one. The new encoding was only added with revision 3 of the architecture or thereabouts, so not so long ago. It used to be reserved previously, so we just handled it arbitrarily (though perhaps we should have panicked instead on encountering it indeed). > I guess it only covers a rather esotheric cache configuration. > > I wonder what variant of the 4Kc is affected by this? So far none has > an I-cache with only 32 lines per way. It must be a recent addition; is the 4Kc maintained anymore actually? I've thought it was replaced with the 4KEc entirely, hmm... Maciej
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