Re: [PATCH 2/2] spi: Add SPI master controller for OCTEON SOCs.

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On 05/13/2012 10:46 PM, Shubhrajyoti Datta wrote:
Hi David,
A few comments.

On Sat, May 12, 2012 at 3:04 AM, David Daney<ddaney.cavm@xxxxxxxxx>  wrote:
[...]

+
+#define DRV_VERSION "2.0" /* Version 1 was the out-of-tree driver */
This could be given a miss. As it is less meaningful once accepted.


Well, this leads to the question, what is the purpose of the 'MODULE_VERSION()' macro? If I use that, I need to populate it with a value.


[...]
+static void octeon_spi_wait_ready(struct octeon_spi *p)
+{
+       union cvmx_mpi_sts mpi_sts;
+       unsigned int loops = 0;
+
+       do {
+               if (loops++)
+                       __delay(500);
Could we allow  have a non-busy loop here?


We could, but I thought about it and chose not to.

The SPI hardware can queue a maximum of 9 bytes (72 bits) before software has to take action. That works out to 3.6 uS at a 20MHz clock rate. Sleeping, scheduling to a different task, taking an interrupt and then switching back to this task will likely not be faster than that.

At lower clock rates, it would make more sense, but it adds complexity to the driver. We can always revisit this decision if it proves to be a problem.

David Daney



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