[PATCH 3/8] MIPS: OCTEON: Fix GPIO interrupt configuration.

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From: David Daney <david.daney@xxxxxxxxxx>

The GPIO bit number is a fixed displacement (16) from the
corresponding CIU bit, and has no relation to the irq number nor
OCTEON_IRQ_GPIO0.

Signed-off-by: David Daney <david.daney@xxxxxxxxxx>
---
 arch/mips/cavium-octeon/octeon-irq.c |   25 +++++++++++++++++--------
 1 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index f3d27ec..4d424ea 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -511,9 +511,11 @@ static void octeon_irq_ciu_enable_all_v2(struct irq_data *data)
 static void octeon_irq_gpio_setup(struct irq_data *data)
 {
 	union cvmx_gpio_bit_cfgx cfg;
-	int bit = data->irq - OCTEON_IRQ_GPIO0;
+	union octeon_ciu_chip_data cd;
 	u32 t = irqd_get_trigger_type(data);
 
+	cd.p = irq_data_get_irq_chip_data(data);
+
 	cfg.u64 = 0;
 	cfg.s.int_en = 1;
 	cfg.s.int_type = (t & IRQ_TYPE_EDGE_BOTH) != 0;
@@ -523,7 +525,7 @@ static void octeon_irq_gpio_setup(struct irq_data *data)
 	cfg.s.fil_cnt = 7;
 	cfg.s.fil_sel = 3;
 
-	cvmx_write_csr(CVMX_GPIO_BIT_CFGX(bit), cfg.u64);
+	cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.bit - 16), cfg.u64);
 }
 
 static void octeon_irq_ciu_enable_gpio_v2(struct irq_data *data)
@@ -548,24 +550,31 @@ static int octeon_irq_ciu_gpio_set_type(struct irq_data *data, unsigned int t)
 
 static void octeon_irq_ciu_disable_gpio_v2(struct irq_data *data)
 {
-	int bit = data->irq - OCTEON_IRQ_GPIO0;
-	cvmx_write_csr(CVMX_GPIO_BIT_CFGX(bit), 0);
+	union octeon_ciu_chip_data cd;
+
+	cd.p = irq_data_get_irq_chip_data(data);
+	cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.bit - 16), 0);
 
 	octeon_irq_ciu_disable_all_v2(data);
 }
 
 static void octeon_irq_ciu_disable_gpio(struct irq_data *data)
 {
-	int bit = data->irq - OCTEON_IRQ_GPIO0;
-	cvmx_write_csr(CVMX_GPIO_BIT_CFGX(bit), 0);
+	union octeon_ciu_chip_data cd;
+
+	cd.p = irq_data_get_irq_chip_data(data);
+	cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.bit - 16), 0);
 
 	octeon_irq_ciu_disable_all(data);
 }
 
 static void octeon_irq_ciu_gpio_ack(struct irq_data *data)
 {
-	int bit = data->irq - OCTEON_IRQ_GPIO0;
-	u64 mask = 1ull << bit;
+	union octeon_ciu_chip_data cd;
+	u64 mask;
+
+	cd.p = irq_data_get_irq_chip_data(data);
+	mask = 1ull << (cd.s.bit - 16);
 
 	cvmx_write_csr(CVMX_GPIO_INT_CLR, mask);
 }
-- 
1.7.2.3




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