[PATCH 0/8] MIPS: OCTEON: Interrupt controller enhancements.
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From: David Daney <david.daney@xxxxxxxxxx> These patches are meant to be applied on top of: http://www.linux-mips.org/archives/linux-mips/2012-03/msg00159.html http://www.linux-mips.org/archives/linux-mips/2012-04/msg00169.html http://www.linux-mips.org/archives/linux-mips/2012-04/msg00173.html The interrupt controller on cn68XX is fundamentally different then on previous members of the OCTEON family. To support it requires importing new register layout definitions for all OCTEONs. The reason for the patches are roughly as follows: 1) Recognize cnf71xx parts, as they are referred to in ... 2) Updated register definitions for all OCTEON parts. 3) Fix snafu in previous patch set. 4) Rid ourselves of unused OCTEON_IRQ_* definitions. We use the device tree infrastructure to find most irqs now. 5) The OCTEON_IRQ_* definitions we still use need to be augmented for the added number of CPUs and increase in size of other SOC resources. 6) Add cn68XX CIU2 support. 7) Quit using sly tricks to avoid taking locks. These tricks fail with threaded interrupt handlers. 8) Fix !CONFIG_SMP build failure. David Daney (8): MIPS: OCTEON: Add detection of cnf71xx parts. MIPS: OCTEON: Update register definitions. MIPS: OCTEON: Fix GPIO interrupt configuration. MIPS: OCTEON: Get rid of unused OCTEON_IRQ_* definitions. MIPS: OCTEON: Add OCTEON_IRQ_* definitions for cn68XX chips. MIPS: OCTEON: Add support for cn68XX interrupt controller. MIPS: Octeon: Make interrupt controller work with threaded handlers. MIPS: OCTEON: Don't refer to octeon_irq_cpu_offline_ciu() when !CONFIG_SMP
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