Re: [PATCH][MIPS] fix divide by zero error in build_clear_page and build_copy_page | |
| [Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] | |
On Thu, May 08, 2008 at 12:04:54AM +0100, Maciej W. Rozycki wrote: > > > Why would ever cache_line_size be zero in this place? Are you trying to > > > support a cacheless CPU? If not, it should be a BUG_ON(). > > > > > > > When CPU has no prefetch, no cache cdex_s and no caache cdex_p, cache_line_size is zero. > > I confirmed it with Nevada(Cobalt server) and VR41xx. > > Fair enough. I confused the variable with some others used to store the > actual line size of each of the caches. Your change is correct, thank you > and sorry about the noise. And I guess that means the variable should get a better name. Ralf
[Linux MIPS Home] [Kernel list] [Linux ARM list] [Linux] [Git] [Photo] [Yosemite News] [MIPS Architecture] [Linux SCSI] [Linux Hams] [Site Home]
![]() |