RE: [PATCH] xHCI: Correct the #define XHCI_LEGACY_DISABLE_SMI

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Hi Sarah,

No. I just debug another issue of SLE11SP2 and see the codes. I have re-sent
the patch v2 according to your advice. It make sense to avoid some potential
bugs in pci-quirks.c.

Thanks,
Alex

=============================================================================
Does this cause any bugs?  E.g. SMIs when the OS grabs control from the
BIOS?

I'm trying to decide whether to backport this fix to the stable kernels.

> 
> Signed-off-by: Alex He <alex.he@xxxxxxx>
> ---
>  drivers/usb/host/xhci-ext-caps.h |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/usb/host/xhci-ext-caps.h b/drivers/usb/host/xhci-ext-caps.h
> index c7f3312..b9c9ffb 100644
> --- a/drivers/usb/host/xhci-ext-caps.h
> +++ b/drivers/usb/host/xhci-ext-caps.h
> @@ -62,8 +62,8 @@
>  /* USB Legacy Support Control and Status Register  - section 7.1.2 */
>  /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
>  #define XHCI_LEGACY_CONTROL_OFFSET	(0x04)
> -/* bits 1:2, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */
> -#define	XHCI_LEGACY_DISABLE_SMI		((0x3 << 1) + (0xff << 5) + (0x7 << 17))
> +/* bits 1:3, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */
> +#define	XHCI_LEGACY_DISABLE_SMI		((0x7 << 1) + (0xff << 5) + (0x7 << 17))
>  
>  /* USB 2.0 xHCI 0.96 L1C capability - section 7.2.2.1.3.2 */
>  #define XHCI_L1C               (1 << 16)
> -- 
> 1.7.1
> 
> 
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