lh7a40x_udc and s3c2410_udc sharing code

[Matthieu CASTET <matthieu.castet@xxxxxxxxxx>]

Hi,


after a quick look, lh7a40x_udc and s3c2410_udc controller seems quite 
similar.

They differ with some registers differences but the main logic is very 
similar. The 2 controllers probably come from the same API.

I don't know the stability of lh7a40x_udc, but s3c2410_udc is not perfect.

For example s3c2410_udc seems to miss some interrupt and need to read rx 
fifo until the fifo is empty.
That's what does the (still uncommitted) patch from Matt Reimer[1].


But if we look in lh7a40x_out_epn from lh7a40x_udc.c, it does already that.

It is also quite messy. For example there a lot's of unneeded 
S3C2410_UDC_INDEX_REG. [2]



I wonder if using the lh7a40x_udc logic for s3c2410_udc, or even sharing 
the common part, won't improve stability for s3c2410_udc driver.


Matthieu


[1] 
http://article.gmane.org/gmane.linux.usb.devel/59315/match=s3c2410+usb+gadget+problems+file+storage

[2]
s3c2410_udc_ep_enable :

[...]
local_irq_save (flags);
[...]
         udc_write(ep->num, S3C2410_UDC_INDEX_REG);
         udc_write(csr1, S3C2410_UDC_IN_CSR1_REG);
         udc_write(ep->num, S3C2410_UDC_INDEX_REG);
         udc_write(csr2, S3C2410_UDC_IN_CSR2_REG);

         csr1 = S3C2410_UDC_OCSR1_FFLUSH | S3C2410_UDC_OCSR1_CLRDT;
         csr2 = S3C2410_UDC_OCSR2_DMAIEN;

         udc_write(ep->num, S3C2410_UDC_INDEX_REG);
         udc_write(csr1, S3C2410_UDC_OUT_CSR1_REG);
         udc_write(ep->num, S3C2410_UDC_INDEX_REG);
         udc_write(csr2, S3C2410_UDC_OUT_CSR2_REG);
[...]

That's 4 write to S3C2410_UDC_INDEX_REG, but we need to select it only once.

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