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Re: [PATCH 0/4] pch_uart: Cleanups, board quirks, and user uartclk parameter

On 02/22/2012 12:58 AM, Alan Cox wrote:
>>> assume a 192 MHz clock on all boards. The problem with this approach is
>>> that the CLKCFG register may have been set to something other than the
>>> 192MHz configuration by the firmware.
> So you can use the early PCI hooks or even bash the register directly in
> your early bootup code. You won't be the only early boot console that
> does this sort of thing. There are even people bitbanging PCI I²C
> interfaces at boot time for such purpose.
>> So, I think default uart_clock 192MHz setting is better than Darren's opinion.
> It's certainly easier to maintain, but it would be good to know if the
> setting can be written or retrieved directly in the early console setup
> using the early PCI ops or similar.

OK, I'm not opposed to forcing everything to 192MHz, that would clean up
pch_uart.c quite a bit. I have heard different things about the
specification for this chipset. One statement was that 64MHz was the
maximum UART clock. Feng suggests that 192MHz is the recommended UART
clock. I need to dig up this spec and determine what it actually says.

I have V2 with Alan's feedback from 2/4 incorporated, but I'll hold off
unless people want to see it now. Seems like it will change a lot if we
force 192MHz everywhere.

Darren Hart
Intel Open Source Technology Center
Yocto Project - Linux Kernel
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