RE: designware: RC BARs setup related fix

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+Cc linux-pci@xxxxxxxxxxxxxxx

> -----Original Message-----
> From: Mohit KUMAR DCG
> Sent: Wednesday, February 05, 2014 10:06 AM
> To: 'Jingoo Han'
> Cc: Arnd Bergmann (arnd@xxxxxxxx); Pratyush ANAND
> Subject: designware: RC BARs setup related fix
> 
> Hello Jingoo,
> 
> The Synopsys  PCIe core provides one pair of 32-bit BARs (BAR 0 and BAR 1).
> The BARs can  be configured as follows:
> - One 64-bit BAR: BARs 0 and 1 are combined to form a single 64-bit BAR.
> - Two 32-bit BARs: BARs 0 and 1 are two independent 32-bit BARs
> 
> For the 64-bit, non-prefetchable memory BAR configuration should be:
> 	/* setup RC BARs */
> 	dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
> 	dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1);
> 
> For 32-bit, non-prefetchable memory BAR configuration should be:
> 	/* setup RC BARs */
> 	dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_0);
> 	dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1);
> 
> While reviewing the code I find that dw driver programmed BARs as:
> 	/* setup RC BARs */
> 	dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
> 	dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_1);
> 
> I think it needs to be fixed. If you agree I will fix it as in option 1 or you  have
> some  other point?
> 
> Thanks
> Mohit
> 

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