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Re: video capture driver interlacing question (easycap)



On Thu, Apr 26, 2012 at 5:33 PM, Ezequiel García <elezegarcia@xxxxxxxxx> wrote:
> Hi everyone,
>
> As you may know I'm re-writing from scratch the staging/easycap driver.
>
> Finally, after digging through the labyrinthic staging/easycap code,
> I've reached a point where I'm able to understand isoc packets.
> Despite not having any documentation (I asked several times) from chip vendor,
> I can separate packets in odd and even.
>
> So, instead of receiving frames the device is sending me fields, right?
>
> My doubt now is this:
> * Do I have to *merge* this pair of fields for each frame, or can I
> give it to v4l?
> If affirmative: how should I *merge* them?
> * Is this related to multiplanar buffers (should I use vb2_plane_addr)?
>
> Currently, staging/easycap does some strange and complex conversion,
> from the pair of fields buffers, to get a "frame" buffer (!) but I'm
> not sure if it's the correct way to do it?
>
> I guess I can keep staring at em28xx (together with vivi/uvc/pwc) driver,
> but if someone cares to give me a small hint or point me at a small portion
> of code I'll be grateful.
>
> Thanks,
> Ezequiel.

Anyone?
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