Re: [PATCH v3 2/2] staging: iio: light: isl29018: use regmap for register access

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On Friday 20 April 2012 01:26 AM, Lars-Peter Clausen wrote:
On 04/19/2012 09:27 PM, Laxman Dewangan wrote:
On Thursday 19 April 2012 11:22 PM, Grant Grundler wrote:
On Thu, Apr 19, 2012 at 4:15 AM, Laxman
Dewangan<ldewangan@xxxxxxxxxx>   wrote:
+static bool is_volatile_reg(struct device *dev, unsigned int reg)
+{
+       switch (reg) {
+       case ISL29018_REG_ADD_DATA_LSB:
+       case ISL29018_REG_ADD_DATA_MSB:
+       case ISL29018_REG_ADD_COMMAND1:
+       case ISL29018_REG_TEST:
Of these four, I think only ADD_COMMAND1 wasn't treated as volatile in
the old code. Am I overlooking something?

My concern is only about the additional I2C read traffic this patch
might generate. It's possible *some* bits in that register are
volatile and we could previously ignore them.

Register ADD_COMMAND1, bit 2 is interrupt flag bit which shows the
interrupt status and hence we can not cache it.
The ISL29018 datasheet says:
Interrupt flag; Bit 2. This is the status bit of the interrupt.
The bit is set to logic high when the interrupt thresholds
have been triggered, and logic low when not yet triggered.
Once triggered, INT pin stays low and the status bit stays
high. Both interrupt pin and the status bit are automatically
cleared at the end of Command Register I transfer.
If the bit is cleared when reading the register I suppose it is not being worth
much to mark the register as volatile since the bit will be cleared whenever
you update the register. If there is only opmode and the irq bit in that
register I'd keep the register volatile, but use regmap_write instead of
regmap_update_bits.

There is 2-bits in ADD_COMMAND1  for interrupt persistence.
The interrupt pin and the interrupt flag is triggered/set when the data sensor
reading is out of the interrupt threshold window after m
consecutive number of integration cycles.


The driver is not supporting interrupt now. I think we can use regmap_write() in place of regmap_update_bits() keeping this volatile as you suggested. When we add interrupt support on this driver, we will write the register after ORing with persistence bits. For that also it will not require to do caching of register.

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