Re: [PATCH 2/2]Add Variable Page Size and IA64 Support in Intel IOMMU: IA64 Specific Part

[Bjorn Helgaas <bjorn.helgaas@xxxxxx>]

On Thursday 02 October 2008 11:46:04 am Yu, Fenghua wrote:
> >> --- a/arch/ia64/include/asm/cacheflush.h
> >> +++ b/arch/ia64/include/asm/cacheflush.h
> >> @@ -34,6 +34,8 @@ do {                                                \
> >>  #define flush_dcache_mmap_unlock(mapping)    do { } while (0)
> >>
> >>  extern void flush_icache_range (unsigned long start, unsigned long end);
> >> +extern void clflush_cache_range(void *addr, int size);
> >
> >This patch adds clflush_cache_range(), but it's not used anywhere.
> Clflush_cache_range() is used in __iommu_flush_cache() in include/linux/intel-iommu.h.

Oh, OK.  I didn't look hard enough to find __iommu_flush_cache()
(currently in drivers/pci/intel-iommu.c).

Architecturally, I'm surprised that ia64 would need to actually do a
cache flush.  I would think the VT-d hardware would do coherent accesses
which would make the cache flush unnecessary.

Bjorn
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