The patchset contains updates to the MCE driver based on the Scalable MCA specification. Patches 1-3 include some minor changes to existing code and have been tested for regressions on older families. Patches 4-5 is new code and only runs on processors with ScalableMCA feature enabled (for future) Patch 1: Order of mce_amd_feature_init() was incorrect as it should be called after we gather features from cpuid bits. Fixing that in this patch Patch 2: We do not require shared bank verification on ZP. Modifying code here to return early if we are on a processor that supports SMCA feature. Patch 3: The number of blocks per bank is reduced from Fam17h onwards. Fixing code to reflect this architectural change Patch 4: LVT offset for thresholding is now programmed in different MSR as opposed to per-bank MISC register in earlier processors. Fixing code here to obtain LVT offset from correct MSR. Patch 5: OS is required to set MCAXEn bit in the per-bank CONFIG MSR to acknowledge the use of new MSR range for MCA. Doing that here and also creating definitions for the new MSR range in msr-index. Note: checkpatch generates warnings for Patch 5. But I have not wrapped text around the character limit as it looked ugly. (I overshot it by only a character or two) Aravind Gopalakrishnan (5): x86, mce: Fix order of AMD MCE init function call x86/mcheck/AMD: Do not perform shared bank check for future processors x86/mcheck/AMD: Reduce number of blocks scanned per bank x86/mcheck/AMD: Fix LVT offset configuration for thresholding x86/mcheck/AMD: Set MCAX Enable bit arch/x86/include/asm/msr-index.h | 23 +++++++++++++++++ arch/x86/kernel/cpu/mcheck/mce.c | 2 +- arch/x86/kernel/cpu/mcheck/mce_amd.c | 50 ++++++++++++++++++++++++++++++++++-- 3 files changed, 72 insertions(+), 3 deletions(-) -- 2.7.0 -- To unsubscribe from this list: send the line "unsubscribe linux-edac" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html