[PATCH 0/3] Optimized RFC4106 AES-GCM implementation using Intel New Instructions

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Hello,

This set of patches adds an optimized RFC4106 AES-GCM implementation for 64-bit kernels and 128-bit AES keys. It supports processors based on the Intel(r) microarchitecture codename Westmere, such as the Intel(r) Xeon(r) 5600 processor family.

The code leverages the crypto AEAD interface type to facilitate a combined AES & GCM operation to be implemented in a unified block of assembly code. The assembly code leverages Intel(r) AES New Instructions and the carry-less multiple PCLMULQDQ instruction which were introduced on the Intel(r) microarchitecture codename Westmere.

The first patch is an update to the cryptd framework to add support for the AEAD interface type.
The second patch is the RFC4106 AES-GCM Crypto Driver & Assembly Code. 
The third patch is an update to crypto self-test code to extend AES-GCM tests.

For more information on the patches, the assembly code design, and on some performance results please reference these papers:
Using Intel(r) AES New Instructions and PCLMULQDQ to Significantly Improve IPSec Performance on Linux: http://download.intel.com/design/intarch/papers/324238.pdf
Optimized Galois-Counter-Mode Implementation on Intel(r) Architecture Processors: http://download.intel.com/design/intarch/PAPERS/324194.pdf

Regards,
Adrian Hoban
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