Re: [PATCH 1/2] KVM: PPC: bookehv: Fix r8/r13 storing in level exception handler

[Alexander Graf <agraf@xxxxxxx>]

On 16.04.2012, at 16:08, Mihai Caraman wrote:

> Guest r8 register is held in the scratch register and stored correctly,
> so remove the instruction that clobbers it. Guest r13 was missing from vcpu,
> store it there.
> 
> Signed-off-by: Mihai Caraman <mihai.caraman@xxxxxxxxxxxxx>
> ---
> arch/powerpc/kvm/bookehv_interrupts.S |    2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S
> index 0d04bc9..0ca987d 100644
> --- a/arch/powerpc/kvm/bookehv_interrupts.S
> +++ b/arch/powerpc/kvm/bookehv_interrupts.S
> @@ -264,10 +264,10 @@ _GLOBAL(kvmppc_handler_\intno\()_\srr1)
> 	mfspr	r6, \srr1
> 	PPC_LL	r4, GPR11(r8)
> 	PPC_STL	r7, VCPU_GPR(r7)(r11)
> -	PPC_STL	r8, VCPU_GPR(r8)(r11)

I'm not sure I can follow you here. The code that leads up to this is:

#define NORMAL_EXCEPTION_PROLOG(intno)                                               \
        mtspr   SPRN_SPRG_WSCRATCH0, r10;       /* save one register */      \
        mfspr   r10, SPRN_SPRG_THREAD;                                       \
        stw     r11, THREAD_NORMSAVE(0)(r10);                                \
        stw     r13, THREAD_NORMSAVE(2)(r10);                                \
        mfcr    r13;                    /* save CR in r13 for now          */\
        mfspr   r11, SPRN_SRR1;                                              \
        DO_KVM  BOOKE_INTERRUPT_##intno SPRN_SRR1;                           \

[...]

.macro DO_KVM intno srr1
#ifdef CONFIG_KVM_BOOKE_HV
BEGIN_FTR_SECTION
        mtocrf  0x80, r11       /* check MSR[GS] without clobbering reg */
        bf      3, kvmppc_resume_\intno\()_\srr1
        b       kvmppc_handler_\intno\()_\srr1
kvmppc_resume_\intno\()_\srr1:
END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
#endif
.endm

[...]

So where is r8 held in a scratch register here? The only registers that I can see stored in scratch registers are r10, r11, r13


> 	PPC_STL r3, VCPU_GPR(r10)(r11)
> 	mfctr	r7
> 	PPC_STL	r12, VCPU_GPR(r12)(r11)
> +	PPC_STL r13, VCPU_GPR(r13)(r11)

r13 however is in a scratch register / scratch memory location according to the code above :).


Alex

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