[PATCH 19/30] KVM: PPC: e500mc: add load inst fixup

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There's always a chance we're unable to read a guest instruction. The guest
could have its TLB mapped execute-, but not readable, something odd happens
and our TLB gets flushed. So it's a good idea to be prepared for that case
and have a fallback that allows us to fix things up in that case.

Add fixup code that keeps guest code from potentially crashing our host kernel.

Signed-off-by: Alexander Graf <agraf@xxxxxxx>
 arch/powerpc/kvm/bookehv_interrupts.S |   30 +++++++++++++++++++++++++++++-
 1 files changed, 29 insertions(+), 1 deletions(-)

diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S
index 63023ae..e0f484c 100644
--- a/arch/powerpc/kvm/bookehv_interrupts.S
+++ b/arch/powerpc/kvm/bookehv_interrupts.S
@@ -28,6 +28,7 @@
 #include <asm/asm-compat.h>
 #include <asm/asm-offsets.h>
 #include <asm/bitsperlong.h>
+#include <asm/thread_info.h>
 #include "../kernel/head_booke.h" /* for THREAD_NORMSAVE() */
@@ -171,9 +172,36 @@
 	PPC_STL	r30, VCPU_GPR(r30)(r4)
 	PPC_STL	r31, VCPU_GPR(r31)(r4)
 	mtspr	SPRN_EPLC, r8
+	/* disable preemption, so we are sure we hit the fixup handler */
+#ifdef CONFIG_PPC64
+	clrrdi	r8,r1,THREAD_SHIFT
+	rlwinm	r8,r1,0,0,31-THREAD_SHIFT       /* current thread_info */
+        lwz     r6,TI_PREEMPT(r8)
+	addi	r7,r6,1
+        stw     r7,TI_PREEMPT(r8)
-	lwepx	r9, 0, r5
+	/*
+	 * In case the read goes wrong, we catch it and write an invalid value
+	 * in LAST_INST instead.
+	 */
+1:	lwepx	r9, 0, r5
+.section .fixup, "ax"
+	b 2b
+.section __ex_table,"a"
+	PPC_LONG 1b,3b
 	mtspr	SPRN_EPLC, r3
+        stw     r6,TI_PREEMPT(r8)
 	stw	r9, VCPU_LAST_INST(r4)

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