Re: [PATCH] KVM: Qemu: Flush i-cache after ide-dma operation in IA64

[tgingold@xxxxxxx]

Quoting Avi Kivity <avi@xxxxxxxxxx>:

> Zhang, Yang wrote:
> > The data from dma will include instructions. In order to exeuting the right
> > instruction, we should to flush the i-cache to ensure those data can be see
> > by cpu.
> >
> >
> >
> > diff --git a/qemu/cache-utils.h b/qemu/cache-utils.h
> > index b45fde4..5e11d12 100644
> > --- a/qemu/cache-utils.h
> > +++ b/qemu/cache-utils.h
> > @@ -33,8 +33,22 @@ static inline void flush_icache_range(unsigned long
> start, unsigned long stop)
> >      asm volatile ("sync" : : : "memory");
> >      asm volatile ("isync" : : : "memory");
> >  }
> > +#define qemu_sync_idcache flush_icache_range
> > +#else
> >
> > +#ifdef __ia64__
> > +static inline void qemu_sync_idcache(unsigned long start, unsigned long
> stop)
> > +{
> > +    while (start < stop) {
> > +	    asm volatile ("fc %0" :: "r"(start));
> > +	    start += 32;
> > +    }
> > +    asm volatile (";;sync.i;;srlz.i;;");
> > +}
> >

As I hit the same issue a year ago, here is my understanding:

> What about smp?

fc will broadcast to the coherence domain the cache invalidation.  So it is
SMP-ready for usual machines.

> I'm surprised the guest doesn't do this by itself?

It doesn't had to do it.  The PCI transaction will automatically invalidate
caches - but qemu doesn't emulate this (and doesn't need to do on x86).

Tristan.
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