[Android-virt] [RFC PATCH 5/6] fixup! ARM: KVM: World-switch implementation

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On Wed, Jun 27, 2012 at 6:04 AM, Marc Zyngier <marc.zyngier at arm.com> wrote:
> On 27/06/12 10:47, Alexander Graf wrote:
>>
>>
>> On 27.06.2012, at 11:23, Marc Zyngier <marc.zyngier at arm.com> wrote:
>>
>>> Hi Christoffer,
>>>
>>> On 26/06/12 23:24, Christoffer Dall wrote:
>>>> Signed-off-by: Christoffer Dall <c.dall at virtualopensystems.com>
>>>> ---
>>>> arch/arm/kvm/interrupts.S | ? ?6 +++---
>>>> 1 file changed, 3 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/arch/arm/kvm/interrupts.S b/arch/arm/kvm/interrupts.S
>>>> index 625ba6c..d1a9b75 100644
>>>> --- a/arch/arm/kvm/interrupts.S
>>>> +++ b/arch/arm/kvm/interrupts.S
>>>> @@ -271,9 +271,9 @@ ENDPROC(__kvm_flush_vm_context)
>>>> ?* (hardware reset value is 0) */
>>>> .macro set_hstr entry
>>>> ? ?mrc ? ?p15, 4, r2, c1, c1, 3
>>>> - ? ?ldr ? ?r3, =0x8e00
>>>> + ? ?ldr ? ?r3, =0x00108e00
>>>
>>> Where does this value comes from? In my copy of the ARM ARM, bits
>>> 31:18,14,4 of HSTR are reserved.

yes, complete brain damage, thanks for pointing this out.

>>
>> Speaking of which, any reason to not use proper constant #defines here, so that this number makes any sense at all? :)
>
> So you really want maintainable code? Heretic! ;-)
>

a little unsure what we should do with the CPACR (are there
potentially other coprocessors that we need to take care of and
switch, or...?) and correspondingly what to do with TCPAC, TASE, and
TCPn (except for the VFP patch already in the works). If we trap all
the coproc accesses, TASE, or TCPAC the guest dies on undefined
exceptions (after the latest patch). Marc?

what I really meant was, of course, this:


diff --git a/arch/arm/include/asm/kvm_arm.h b/arch/arm/include/asm/kvm_arm.h
index 8976e0d..5365ddc 100644
--- a/arch/arm/include/asm/kvm_arm.h
+++ b/arch/arm/include/asm/kvm_arm.h
@@ -108,6 +108,17 @@
 #define TTBCR_T0SZ	3
 #define HTCR_MASK	(TTBCR_T0SZ | TTBCR_IRGN0 | TTBCR_ORGN0 | TTBCR_SH0)

+/* Hyp System Trap Register */
+#define HSTR_T(x)	(1 << x)
+#define HSTR_TTEE	(1 << 16)
+#define HSTR_TJDBX	(1 << 17)
+
+/* Hyp Coprocessor Trap Register */
+#define HCPTR_TCP(x)	(1 << x)
+#define HCPTR_TCP_MASK	(0x3fff)
+#define HCPTR_TASE	(1 << 15)
+#define HCPTR_TTA	(1 << 20)
+#define HCPTR_TCPAC	(1 << 31)

 /* Virtualization Translation Control Register (VTCR) bits */
 #define VTCR_SH0	(3 << 12)
diff --git a/arch/arm/kvm/interrupts.S b/arch/arm/kvm/interrupts.S
index 625ba6c..ab56812 100644
--- a/arch/arm/kvm/interrupts.S
+++ b/arch/arm/kvm/interrupts.S
@@ -271,7 +271,7 @@ ENDPROC(__kvm_flush_vm_context)
  * (hardware reset value is 0) */
 .macro set_hstr entry
 	mrc	p15, 4, r2, c1, c1, 3
-	ldr	r3, =0x8e00
+	ldr	r3, =(HSTR_T(9) | HSTR_T(10) | HSTR_T(11) | HSTR_T(15))
 	.if \entry == 1
 	orr	r2, r2, r3		@ Trap CR{9,10,11,15}
 	.else
@@ -280,6 +280,19 @@ ENDPROC(__kvm_flush_vm_context)
 	mcr	p15, 4, r2, c1, c1, 3
 .endm

+/* Configures the HCPTR (Hyp Coprocessor Trap Register) on entry/return
+ * (hardware reset value is 0) */
+.macro set_hcptr entry
+	mrc	p15, 4, r2, c1, c1, 2
+	ldr	r3, =(HCPTR_TTA)
+	.if \entry == 1
+	orr	r2, r2, r3		@ Trap some coproc-accesses
+	.else
+	bic	r2, r2, r3		@ Don't trap any coproc- accesses
+	.endif
+	mcr	p15, 4, r2, c1, c1, 2
+.endm
+
 /* Enable/Disable: stage-2 trans., trap interrupts, trap wfi, trap smc */
 .macro configure_hyp_role entry, vcpu_ptr
 	mrc	p15, 4, r2, c1, c1, 0	@ HCR
@@ -326,8 +339,9 @@ ENTRY(__kvm_vcpu_run)
 	@ Configure Hyp-role
 	configure_hyp_role 1, r0

-	@ Trap coprocessor CRx for all x except 2 and 14
+	@ Trap coprocessor CRx accesses
 	set_hstr 1
+	set_hcptr 1

 	@ Write configured ID register into MIDR alias
 	ldr	r1, [r0, #VCPU_MIDR]
@@ -375,6 +389,7 @@ __kvm_vcpu_return:

 	@ Don't trap coprocessor accesses for host kernel
 	set_hstr 0
+	set_hcptr 0

 	@ Reset Hyp-role
 	configure_hyp_role 0, r1
---

Thanks,
Christoffer



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