Re: Unable to remove pipeline stalls

[Ian Lance Taylor <iant@xxxxxxxxxx>]

On Wed, Jul 18, 2012 at 2:19 AM, Deepti Sharma
<deepti.gccretarget@xxxxxxxxx> wrote:
>
> I am facing one issue with pipeline stalls. My compiler generates below
> assembly:
>  MOVE AR2, _rec2
>  MOVE AR0, _rec1
>  MOVE R3, (AR2)+  //Writes to R3
>  MOVE (AR0)+, R3  //Reads from R3; Stall Created
>  MOV  AR1, AR0
>  MOV  AR0, AR2
>  MOVE R2, (AR0)+  //
>  MOVE (AR1)+, R2  // stall
>  MOVE R1, (AR0)+  //
>  MOVE (AR1)+, R1  // stall
>  MOVE R0, (AR0,0)
>  MOVE (AR1,0), R0  //stall

...

> ;;   ======================================================
> ;;   -- basic block 2 from 7 to 20 -- before reload
> ;;   ======================================================
>
> ;;        0-->     7 r62=`r1'
> ;;        1-->     8 r63=`r2'                          :UNIT3
> ;;        2-->    11 [r62++]=[r63++]                   :UNIT1|UNIT2
> ;;        3-->    12 r65=r62                           :UNIT4
> ;;        4-->    13 r64=r63                           :UNIT4
> ;;        5-->    14 [r65++]=[r64++]                   :UNIT1|UNIT2
> ;;        6-->    17 [r65++]=[r64++]                   :UNIT1|UNIT2
> ;;        7-->    20 [r65]=[r64]                       :UNIT1|UNIT2
>
> Any pointers for this issue will be helpful.

I don't understand how insns like [r65++]=[r64++] correspond to the
assembler instruction sequence you show above.  Do you have a
define_split in there that only happens after reload is complete?
Perhaps you need to be looking at the scheduler dump after reload,
which is to say the one from -fschedule-insns2.

Ian