DSR interruptible by scheduler + memory barriers
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Hello,unfortunately I couldn't find the answer in the documentation. If the scheduler runs a DSR. Can this DSR become interrupted by an other thread or another DSR? (Of cause an ISR can interrupt it)
The background is that I wanna share data between a thread an a DSR and want to know whether I have to call cyg_(un)lock_scheduler when changing the data.
And another question about that - how are memory barriers implemented in eCos? (Are they implemented at all?) Background: I have - for example - a status bit field that is copied to a (ISR/DSR) shared variable in the ISR. Now - if the compiler decides to put this variable into a register (in the ISR function) the DSR will get the wrong data. I could of cause declare the variable as volatile but this might be a performance issue in other cases where more data is affected.
Best regards, Martin Laabs -- Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss