Re: ecos-3.0 current stm32 bug?
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On 08/25/2011 12:37 PM, Nick Garnett wrote:
On 25/08/11 09:48, Philipp Meier wrote:Hello Christophe it is the SWI instruction ("svc 0" in disassem code) that triggers the exception (therefore breakpoint in hal_switch_state_vsr is never reached). Where does the SWI instruction get's it's information about where to jump to? Is it the hal_vsr_table (located at 0x20000000)? In entry 11 I have 0x8040025 which is the address for hal_switch_state_vsr - and yet it does not jumps to 0x8040025 but instead to 0x8040042 (hal_default_exception_vsr). Any idea about the reason for this behaviour?The SWI is probably causing the CPU to take a HardFault exception because BASEPRI is higher than the priority of the SWI exception. If I understand correctly, both your bootloader and application are configured for ROM startup. The ROM startup code in hal_misc.c expects to find the CPU in its initial state. When your application runs, the bootloader has already run this code and put it into a different state, which will then cause the SWI to throw a HardFault. For your application you really need a new startup type that does the RAM initialization parts of a ROM startup, but omits parts of the hardware initialization.
Yes you are right - that's the case.With the bootloader built under Windows/Cygwin, basepri (mon reg basepri) is 0x00 when my application's hal_reset_vsr function is reached. When I build the bootloader (using the same ecos-library version/code and the same bootloader source code) under Linux, then basepri is 0x10 when my application's hal_reset_vsr function is reached.
Why this difference between Cygwin and Linux? -- Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss