Re: ecos-3.0 current stm32 bug?
|[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]|
On 25/08/11 09:48, Philipp Meier wrote: > Hello Christophe > > it is the SWI instruction ("svc 0" in disassem code) that triggers the exception (therefore breakpoint in hal_switch_state_vsr is never reached). > > Where does the SWI instruction get's it's information about where to jump to? Is it the hal_vsr_table (located at 0x20000000)? In entry 11 I have 0x8040025 which is the address for hal_switch_state_vsr - and yet it does not jumps to 0x8040025 but instead to 0x8040042 (hal_default_exception_vsr). > > Any idea about the reason for this behaviour? The SWI is probably causing the CPU to take a HardFault exception because BASEPRI is higher than the priority of the SWI exception. If I understand correctly, both your bootloader and application are configured for ROM startup. The ROM startup code in hal_misc.c expects to find the CPU in its initial state. When your application runs, the bootloader has already run this code and put it into a different state, which will then cause the SWI to throw a HardFault. For your application you really need a new startup type that does the RAM initialization parts of a ROM startup, but omits parts of the hardware initialization. -- Nick Garnett eCos Kernel Architect eCosCentric Limited http://www.eCosCentric.com The eCos experts Barnwell House, Barnwell Drive, Cambridge, UK. Tel: +44 1223 245571 Registered in England and Wales: Reg No: 4422071 -- Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss