bttv driver questions

[Jean Delvare <jdelvare@xxxxxxx>]

Hi Mauro, hi Trent,

I'm back with more questions about the bttv driver:

* When is the bttv IRQ handler called? At the end of every frame? At
  the end of the VBI? Between the odd field and even field sequences
  for full resolution frames?

* Does the bttv driver have anything special to do for full
  resolution frames, that it doesn't have to do for half resolution
  ones? In particular, I wonder if the BT878 DMA engine knows how to
  interlace fields when writing to the memory, or if the bttv driver
  must take care of reordering the fields properly afterwards. I
  suspect the latter.

* How longs are the blocks written by the BT878 DMA engine to memory?
  Obviously it can't send more than the FIFO size (128 bytes) at
  once. With the default PCI latency value (32) it seems that a
  maximum of 96 bytes can actually be sent at once (8 cycles for
  setup and 24 cycles for data on a 32-bit PCI bus -> 96 bytes per
  transfer.) I am curious if there is a minimum FIFO usage for the
  BT878 to request the PCI bus. Couldn't find anything related to
  this in the datasheet.

* In continuation of the above, am I correct assuming that setting
  the latency timer of the BT878 above 40 doesn't make sense? 40 PCI
  cycles is enough to empty the FIFO completely, and then there's no
  data left to send. But I'm curious how the BT878 behaves if it is
  granted more time than it needs. Can it return the PCI bus control
  earlier? Or is it keeping control of the bus and sending more data
  as it becomes (slowly) available? The later would be bad for both
  latency and throughput.

If anyone can help me answer these questions, I would be grateful.
Thanks!

-- 
Jean Delvare
Suse L3

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