Re: PCI resources above 4GB

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On 14/04/12 20:08, Steven Newbury wrote:
> On 14/04/12 19:42, Steven Newbury wrote:
>> On 14/04/12 19:05, Steven Newbury wrote:
>>> On 14/04/12 18:37, Steven Newbury wrote:
>>>> On 12/04/12 17:40, Steven Newbury wrote:
>>>>> On Thu, 12 Apr 2012, 17:07:33 BST, Yinghai Lu 
>>>>> <yinghai@xxxxxxxxxx> wrote:
>>>>>> On Thu, Apr 12, 2012 at 4:22 AM, Steven Newbury 
>>>>>> <steve@xxxxxxxxxxxxxxx> wrote:
>>>>>>> Thanks, that fixed it! :) I had a similar patch I've
>>>>>>> been working on but I had my fix in the wrong place!
>>>>>>> In the working case, initially the BIOS has set GMA to
>>>>>>>  within the low system DRAM 0xC0000000 obviously
>>>>>>> invalid. This conflict is detected and it's
>>>>>>> relallocated to 0x12000000.
>>>>>>> I've attempted to modify probe.c to disable 64-bit
>>>>>>> BARs not allocated above 4G so they get reallocated
>>>>>>> above when possible later.  It seemed to work, but
>>>>>>> again broke GMA despite the BAR originally containing
>>>>>>> an invalid address as mentioned above, it seems for
>>>>>>> some reason something is different when the conflict is
>>>>>>> detected and rellocated, compared to disabling it early
>>>>>>> then allocating a valid value..?
>>>> I've created a new quirk utilising an extra PCI resource
>>>> flag to force reallocation of the resource.  It's the first 
>>>> approach I've had any success at.  It does work.  Only
>>>> "Intel Page Flush" now gets allocated @0xe0000000!
>>> Hopefully this should fix "Intel Flush Page"
>> Need to export pci_bus_alloc_resource_fit for intel-gtt.
> Nearly worked... Or at least it should have worked, but for some 
> reason the allocator failed to utilise 0xe0000000-0xefffffff for 
> 04:00.0 BAR0..?
> pci 0000:03:08.0: BAR 15: can't assign mem pref (size 0x18000000)
Ah! Not enough space for the bridge window!:(

> pci 0000:03:08.0: BAR 14: assigned [mem 0xfef00000-0xfeffffff] pci
> 0000:03:08.0: BAR 13: assigned [io  0x4000-0x4fff] pci
> 0000:04:00.0: BAR 0: can't assign mem pref (size 0x10000000) pci
> 0000:04:00.0: BAR 2: assigned [mem 0xfefe0000-0xfeffffff 64bit] pci
> 0000:04:00.0: BAR 2: set to [mem 0xfefe0000-0xfeffffff 64bit] (PCI 
> address [0xfefe0000-0xfeffffff]) pci 0000:04:00.0: BAR 6: assigned
> [mem 0xfefc0000-0xfefdffff pref] pci 0000:04:00.1: BAR 0: assigned
> [mem 0xfefbc000-0xfefbffff 64bit] pci 0000:04:00.1: BAR 0: set to
> [mem 0xfefbc000-0xfefbffff 64bit] (PCI address
> [0xfefbc000-0xfefbffff]) pci 0000:04:00.0: BAR 4: assigned [io
> 0x4000-0x40ff] pci 0000:04:00.0: BAR 4: set to [io  0x4000-0x40ff]
> (PCI address [0x4000-0x40ff])

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