Re: Viewing page tables and some other questions regarding the MMU

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On Tue, Mar 30, 2010 at 3:56 PM, Leo Barnes <barnes.leo@xxxxxxxxx> wrote:
> Hello!
> I am trying to understand how the ARM MMU works and have a few
> questions that I have so far not been able to find any good answers
> for. My test rigs are a Nokia N810 (ARM1136) and a Nokia N900 (ARM
> Cortex-A8). They are both running Maemo Linux, with my experimentation
> software being loaded as kernel modules so that I can run in
> privileged mode.
> 1. The first thing I would like to do is to view/modify the MMU
> translation tables. I know that the physical addresses of the
> translation tables can be retrieved from the control co-processor, but
> how do I get access to the tables themselves? I hypothesize that in
> order to view or modify the translation tables, the MMU has to be
> disabled.
The MMU does not have to be disabled. To manage the page tables, the
tables themselves must be mapped at some virtual address. In ARM
Linux, this is already done, and you can access the page table entry
for addr by doing something like this:

	pgd_t *pgd;
	pud_t *pud;
	pmd_t *pmd;
	pte_t *pte;

	pgd = pgd_offset(mm, addr);
	pud = pud_alloc(mm, pgd, addr);
	if (!pud) {
		printk(KERN_ERR "Could not alloc pud!\n");
		return NULL;
	pmd = pmd_alloc(mm, pud, addr);
	if (!pmd) {
		printk(KERN_ERR "Could not alloc pmd!\n");
		return NULL;

	pte = pte_alloc_map(mm, pmd, addr);
	if (!pte) {
		printk(KERN_ERR "Could not alloc pte!\n");
		return NULL;

> 2. Does ARM Linux store the translation tables in the format described
> in the ARM reference manuals? I saw some mention about Linux storing
> the translation tables slightly differently than described in the
> manuals, but the forum thread didnt really go into any details. Which
> version of the translation tables are used? Pre v6 or v6?

Well, the page tables must adhere to the architecture specification
since the MMU has to be able to walk the page tables in hardware.
Which version Linux uses depends on the configuration of your specific
kernel. For your N810, it probably uses the VMSAv6. You can check by
looking at the XP bit in the control register at run-time if you
desire. Also, take a look at arch/arm/include/asm/pgtable.h, which
explains how Linux stores additional information for its own use along
with the ARM page tables.

> 3. I notice that there exists a function called ioremap_cached which
> supposedly creates a second, cached, mapping to a physical address.
> How does this work? From what I have read in the ARM manuals, it
> seemed that having two maps to the same physical address with
> different memory attributes was illegal, but this seems to be exactly
> what ioremap_cached does.

I'm not an expert, but I think ioremap is commonly used by device
drivers if they wish to access a device, which is connected at
physical address X through some virtual address Y, by ioremapping Y to

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