Re: Question regarding L2 cache clean.

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On Sun, Aug 23, 2009 at 03:47:37PM +0900, Thomas Abraham wrote:
> This issue is resolved with either of the following two changes.
> 1. L2 cache policy is set to "Cacheable, Write-back, No Write Allocate"
> 2. Perform the cache flush operation twice by repeating the
>     "mcr p15, 0, r0, c7, c10, 1" instruction in v7_dma_clean_range function
>     in the arch/arm/mm/cache-v7.S file.
> The above two changes seems to suggest the L2 cache clean before the DMA
> transfer is not happening. I would like to know if there is any explict L2
> cache flush operation to be performed if L2 cache is set to "Write Allocate"
> mode.

Could you try adding a dsb() call just before the calls to outer_op()
in arch/arm/mm/dma-mapping.c dma_cache_maint() and
dma_cache_maint_contiguous() please?

PS, kernel problems should be sent to the linux-arm-kernel mailing list,
not linux-arm.

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