Question regarding L2 cache clean.

[Thomas Abraham <omas.arm.linux@xxxxxxxxx>]

Hi All,

I am running Linux on a SoC with ARM Cortex A8 r2p2 processor. I have a
question related to the L2 cache clean operation.

I am performing a DMA transfer from external memory to a peripheral
controller. Sometimes, the data moved from memory to the controller is not
correct. The cache clean is performed before the DMA transfer is started.

The following cache policies and being used for L1 and L2 cache.

- L1 cache policy is set to "Cacheable, Write-back, No Write Allocate".
- L2 cache policy is set to "Cacheable, Write-back, Write Allocate".

This issue is resolved with either of the following two changes.

1. L2 cache policy is set to "Cacheable, Write-back, No Write Allocate"
2. Perform the cache flush operation twice by repeating the
    "mcr p15, 0, r0, c7, c10, 1" instruction in v7_dma_clean_range function
    in the arch/arm/mm/cache-v7.S file.

The above two changes seems to suggest the L2 cache clean before the DMA
transfer is not happening. I would like to know if there is any explict L2
cache flush operation to be performed if L2 cache is set to "Write Allocate"
mode.

Thanks for your time and help.

Regards,
Thomas.
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