how to explain the srcpnd and subsrcpnd register of s3c2410x? | |
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Dear all: In the user's manual of S3c2410x, the 14th part about interrupt controller tells two register which are srcpnd and subsrcpnd. Both of them contain INT_ADC bit, how to understand it? In addition, the other 10 bits of subsrcpnd register stand for INT_TC\INT_TXD2\INT_RXD2 .... interrupts request , so if any of them as irq mode really come and asserted by interrupt controller, which bit of INTPND register will be set? anyone can tell me ? thanks a lot ------------------------------------------------------------------- List admin: http://lists.arm.linux.org.uk/mailman/listinfo/linux-arm FAQ: http://www.arm.linux.org.uk/mailinglists/faq.php Etiquette: http://www.arm.linux.org.uk/mailinglists/etiquette.php
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