Re: AT91RM9200 watchdog code

["Andrew Victor" <avictor.za@xxxxxxxxx>]

hi Matt,

> I think the comments should say something to the effect that all
> counting occurs at SLOW_CLOCK / 128 = 256 Hz.

Yes, 256 Hz or 0.256 KHz.
Seems there is a "K" missing in the original comment..

The comment should rather be:
    /*
     * All counting occurs at SLOW_CLOCK / 128 = 256 Hz
     *
     * Since WDV is a 16-bit counter, the maximum period is
     * 65536 / 256 = 256 seconds.
     */

If you have time, please submit a patch to Russell King's patch-tracking system.


Regards.
  Andrew Victor

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