AT91RM9200 watchdog code

["Matt Gessner" <mgessner@xxxxxxxxx>]

Hi,

In linux 2.6.25 (final), I found a couple of comments in
drivers/watchdog/at91rm9200_wdt.c that puzzle me.

In at91_wdt_settimeout, the following comment appears:

/*
 * All counting occurs at SLOW_CLOCK / 128 = 0.256 Hz
 *
 * Since WDV is a 16-bit counter, the maximum period is
 *    65536 / 0.256 = 256 seconds.
 */

It seems like the math is kind of correct, but there's a factor of
1,000 that seems to be missing.

SLOW_CLOCK / 128 = 0.256 ->
SLOW_CLOCK = 128 * .256 ->
SLOW_CLOCK = 32.768 Hz (NOT KHz!)

The docs say XIN32 should be 32.786 KHz (NOT Hz!).

Second, I can't make any sense out of the second comment.

Now, if we assume SLOW_CLOCK is 32.768 KHz, then
          SLOW_CLOCK / 128 = 256 Hz (256 Hz = ~4 ms)

Then, 65536 / 256 = 256 seconds.

But 65536 / 0.256 = 256,000.  If this is off by 1,000 because
SLOW_CLOCK is interpreted as 32.768 Hz (NOT KHz), then it all comes
out in the wash.

And, FWIW, include/asm-arm/arch-at91/hardware.h defines
AT91_SLOW_CLOCK to be 32768.

If this is incorrect, I don't know if it makes ANY sense to change
this.  But I thought I would ask.

I think the comments should say something to the effect that all
counting occurs at SLOW_CLOCK / 128 = 256 Hz.

And that 65536 / 256 Hz = 256 seconds.

It may seem small, but if it puzzles one person, it may puzzle others.

If my math is wrong, would someone kindly show me where I got confused?

If my math is correct, what next?  Is it worth making a change?  I
don't have a current copy of the kernel pulled down, but I could
submit a patch.

Thanks.

Regards,

Matt Gessner

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