[PATCH] ep93xx: add ssp clock

["hartleys" <hartleys@xxxxxxxxxxxxxxxxxxx>]

This patch adds the Synchronous Serial Port clock to the Clock control
for
Cirrus EP93xx chips and initializes the rate for the clock based on the 
EP93xx silicon revision.

It also adds a /proc/clocks interface to output the clocks information.

Signed-off-by: H Hartley Sweeten <hsweeten@xxxxxxxxxxxxxxxxxxx>


--- orig/linux-2.6.25.10/arch/arm/mach-ep93xx/clock.c	2008-07-02
20:46:47.000000000 -0700
+++
/home/bigguiness/buildroot/project_build_arm/ep9307/linux-2.6.25.10/arch
/arm/mach-ep93xx/clock.c	2008-07-18 13:01:54.000000000 -0700
@@ -15,6 +15,7 @@
 #include <linux/err.h>
 #include <linux/module.h>
 #include <linux/string.h>
+#include <linux/proc_fs.h>
 #include <asm/div64.h>
 #include <asm/hardware.h>
 #include <asm/io.h>
@@ -51,6 +52,9 @@ static struct clk clk_usb_host = {
 	.enable_reg	= EP93XX_SYSCON_CLOCK_CONTROL,
 	.enable_mask	= EP93XX_SYSCON_CLOCK_USH_EN,
 };
+static struct clk clk_ssp = {
+	.name		= "sspclk",
+};
 
 
 static struct clk *clocks[] = {
@@ -61,6 +65,7 @@ static struct clk *clocks[] = {
 	&clk_p,
 	&clk_pll2,
 	&clk_usb_host,
+	&clk_ssp,
 };
 
 struct clk *clk_get(struct device *dev, const char *id)
@@ -107,10 +112,10 @@ void clk_put(struct clk *clk)
 }
 
 
-
 static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
 static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
 static char pclk_divisors[] = { 1, 2, 4, 8 };
+static char *ep93xx_rev[] = { "A", "B", "C", "D0", "D1", "E0", "E1",
"E2" };
 
 /*
  * PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) /
2^PS
@@ -130,6 +135,28 @@ static unsigned long calc_pll_rate(u32 c
 	return (unsigned long)rate;
 }
 
+static int
+ep93xx_read_clocks_proc(char *buffer, char **start, off_t offset, int
size,
+		int *eof, void *data)
+{
+	int written = 0;
+	int i;
+
+	if (offset)
+		return 0;
+
+#define OUT(a,b...)	written += snprintf(buffer + written, size -
written, a, ##b)
+
+	OUT("Name                 Rate    Users\n");
+	OUT("----------------  ---------  -----\n");
+	for (i = 0; i < ARRAY_SIZE(clocks); i++) {
+		OUT("%-16s  %9lu  %5d\n",
+			clocks[i]->name, clocks[i]->rate,
clocks[i]->users);
+	}
+
+	return written;
+}
+
 static int __init ep93xx_clock_init(void)
 {
 	u32 value;
@@ -154,11 +181,25 @@ static int __init ep93xx_clock_init(void
 	}
 	clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1);
 
+	/* See http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf */
+	value = __raw_readl(EP93XX_SYSCON_CHIP_ID);
+	value &= 0x0000ffff;
+	if (value < 7)
+		clk_ssp.rate = 14745600/2;
+	else
+		clk_ssp.rate = 14745600;
+
 	printk(KERN_INFO "ep93xx: PLL1 running at %ld MHz, PLL2 at %ld
MHz\n",
 		clk_pll1.rate / 1000000, clk_pll2.rate / 1000000);
 	printk(KERN_INFO "ep93xx: FCLK %ld MHz, HCLK %ld MHz, PCLK %ld
MHz\n",
 		clk_f.rate / 1000000, clk_h.rate / 1000000,
 		clk_p.rate / 1000000);
+	if (value < 8)
+		printk(KERN_INFO "ep93xx: Silicon Rev %s\n",
ep93xx_rev[value]);
+	else
+		printk(KERN_INFO "ep93xx: Silicon Rev unknown (%d)\n",
value);
+
+	create_proc_read_entry("clocks", 0, 0, ep93xx_read_clocks_proc,
NULL);
 
 	return 0;
 } 

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