Re: Cache management

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On Wed, Dec 12, 2007 at 02:00:01PM +0100, Dag-Erling Smørgrav wrote:
> Catalin Marinas <catalin.marinas@xxxxxxx> writes:
> > So, you have an L2 cache. Does you DSP accesses the DRAM directly or
> > through the L2 cache? If the former, does your L2 cache ignore the L1
> > cacheability settings (the C and B bits)?
> The DSP has its *own* L1 and L2 cache.  There is no shared cache, only
> shared DRAM.  The interrupt handler on the DSP flushes and invalidates
> its cache before and after writing to the shared buffer.
> Like I said, I can see the correct values on the ARM side, but my
> interrupt handler (or rather my work queue handler) does not.  I added
> a printk() in there which prints out the old value every time, even
> when I can see from userland that a new value has been written.

Okay, so now you're ignoring me.  That's fine, but when you eventually
come to realise (by actually taking the advice which has been given)
that what I've said was 100% correct, you'll realise that if you had
listened to me in the first place you'd have saved yourself a lot of

That second paragraph above (if accurate) shows that the ARM can see
the right values, but some bug in your work queue handler results in
it seeing corrupted values.

So, if you want people to provide some useful responses, please show
your code.  Otherwise, you're just wasting our time since we need a
crystal ball to work out what you're doing.

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