Re: Cache management

[Catalin Marinas <catalin.marinas@xxxxxxx>]

On Wed, 2007-12-12 at 13:49 +0100, Dag-Erling Smørgrav wrote:> Catalin Marinas <catalin.marinas@xxxxxxx> writes:> > This shouldn't happen unless there is a bug somewhere. What kernel> > version and ARM processor do you use? Do you have any L2 cache? Do you> > set any cachepolicy other than the default?> > 2.6.22.5, ARM926EJ-S, yes, no.
So, you have an L2 cache. Does you DSP accesses the DRAM directly orthrough the L2 cache? If the former, does your L2 cache ignore the L1cacheability settings (the C and B bits)?
-- Catalin

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