Re: Cache management

[Catalin Marinas <catalin.marinas@xxxxxxx>]

On Wed, 2007-12-12 at 12:03 +0100, Dag-Erling Smørgrav wrote:> I am working on setting up two-way communication between the ARM core> and the DSP through shared buffers in DRAM.  These buffers lie outside> the area used by the Linux kernel. I map them into the kernel address> space using ioremap_nocache().> > It turns out that the name of that function is a lie.  The buffers are> in fact cached; to be precise, it seems that they are cached in> write-through mode.  The DSP can see what the ARM writes to the shared> buffer, but the ARM can not see what the DSP sends back.  I have made> sure that the DSP writes back and invalidates its cache before and> after writing to the buffer.
This shouldn't happen unless there is a bug somewhere. What kernelversion and ARM processor do you use? Do you have any L2 cache? Do youset any cachepolicy other than the default?
I would recommend you check the page tables directly to make sure themapping is uncached.
-- Catalin

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