Cache management

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I am working on a device that has an ARM core and a DSP on a shared
memory bus with a shared bank of DRAM.  The ARM core runs a Linux
kernel that uses part of that DRAM (controlled by mem= on the command
line), the DSP runs an application that is configured to use the
remainder (and avoid touching the part used by Linux).  The DSP has no
MMU.

I am working on setting up two-way communication between the ARM core
and the DSP through shared buffers in DRAM.  These buffers lie outside
the area used by the Linux kernel. I map them into the kernel address
space using ioremap_nocache().

It turns out that the name of that function is a lie.  The buffers are
in fact cached; to be precise, it seems that they are cached in
write-through mode.  The DSP can see what the ARM writes to the shared
buffer, but the ARM can not see what the DSP sends back.  I have made
sure that the DSP writes back and invalidates its cache before and
after writing to the buffer.

I have been looking through <asm/cacheflush.h> for something I could
use for a workaround (to flush the cache after writing), but nothing
seems to fit the bill, except flush_cache_all(), which seems like an
evil thing to do.

I am starting to suspect that using ioremap_nocache() in the first
place was a mistake; although there is no practical difference between
DRAM and I/O on this device, there is probably a conceptual difference
from the kernel's point of view which escapes me at the moment.

Does anyone have any advice or suggestions to offer?

DES
-- 
Dag-Erling Smørgrav
Senior Software Developer
Linpro AS - www.linpro.no

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