Re: Buggy at91rm9200 USART?

[Henrik Bork Steffensen <hbs@xxxxxxxxxxxxxxxxx>]

kim M wrote:
> Hi
>
> I have a problem using the period interrupt feature of the USART block
> within the a91rm9100 chip. We have a user space protocol which does
> not behave well when large delays occur between bytes within a
> received frame. Seen from user space: Since the Linux driver uses DMA,
> delays do occur while a DMA buffer is being filled. The delay equals
> the size of the DMA buffer * byte/sec, so at 9600 the delay is in the
> order of 267 msec.
> Therefor, I want to enable the periodic interrupt in the CR register,
> so I can empty the dma buffer before I get timeouts in userspace.
> However, when I do this the drivers spins because I can not clear
> CSR_TIMEOUT.  Well actually what happens is, that as soon at I set the
> the CR_RETTO bit, CSR_TIMEOUT gets asserted.  It doesn't matter how
> high I set the timeout counter - CSR_TIMEOUT is asserted immediately.
> I can clear it by writing CR_STTTO, but then I get no further
> interrupts, and setting CR_RETTO causes another immediate
> interrupt....
>
> So my question is: What is the correct procedure for using the
> CSR(RETTO)  bit in the AT91RM9200 USARTs?
>
> Alternatively, I could disable DMA or adjust the DMA buffer size, but
> using RETTO should work. Does anyone know if this is a known problem?
I would reduce the size of the DMA buffers, they are too large at such a 
low baud rate.
I would reduce them to 16 bytes (16.6 ms), although this might not be 
the perfect solution....

regards,

Henrik Bork Steffensen
RoseTechnology A/S
Denmark


-------------------------------------------------------------------
List admin: http://lists.arm.linux.org.uk/mailman/listinfo/linux-arm
FAQ:        http://www.arm.linux.org.uk/mailinglists/faq.php
Etiquette:  http://www.arm.linux.org.uk/mailinglists/etiquette.php