Re: Write is twice the speed as read?

[Catalin Marinas <catalin.marinas@xxxxxxx>]

"Howe, John" <JHowe@xxxxxxxxxx> wrote:
> Reads are slower than write because the read address request is
> presented on the bus and you wait until the memory mapped device (memory
> or device) data is returned.  Writes are faster because the address and
> data are presented at the same time and is performed in 1 step.

This is partially true. Well, it is true for for non-sequential data
accesses but, once you have the caches enabled or use ldm
instructions, bursts are generated to the multi-port memory controller
(MPMC) and subsequent reads can take a single cycle.

> Read (address, wait, returned data):
> Step 1 - Read request --> Bus --> Device
> Step 2 - data <-- bus <--- device data
> Total of two transactions.

The above is true for a non-sequential access. In this case, step1 can
be much longer (8 cycles) because of the wait states generated by the
memory controller, while the step2 can be 1 cycle only. So, the
difference between reads and writes might not be that big.

Chapter 3 in the VPB926EJ-S_Performance_FAQ_v1_1.pdf document in the
http://www.arm.com/support/VPB926EJ-S_Performance_FAQ_v1_1.zip archive
explains the memory access timings for Versatile/PB. This is also
valid for the Versatile/AB platform since they have the same memory
controller.

-- 
Catalin


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