Hi Santosh, On Mon, Apr 21, 2014 at 07:03:10PM +0100, Santosh Shilimkar wrote: > ARM coherent CPU dma map APIS are assumed to be nops on cache coherent > machines. While this is true, one still needs to ensure that no > outstanding writes are pending in CPU write buffers. To take care > of that, we at least need a memory barrier to commit those changes > to main memory. > > Patch is trying to fix those cases. Without such a patch, you will > end up patching device drivers to avoid the synchronisation issues. Don't you only need these barriers if you're passing ownership of a CPU buffer to a device? In that case, I would expect a subsequent writel to tell the device about the new buffer, which includes the required __iowmb(). That's the reason for the relaxed accessors: to avoid this barrier when it's not needed. Perhaps you're using the relaxed accessors where you actually need the stronger ordering guarantees? Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/linux-arm-kernel