On Sat, Jan 11, 2014 at 4:19 PM, Carlo Caione <carlo.caione@xxxxxxxxx> wrote: > Allwinner A20/A31 SoCs have a special interrupt controller for managing NMI. > Three register are present to (un)mask, control and acknowledge NMI. > These two patches add a new irqchip driver in cascade with GIC. > > Changes since v1: > - added binding document > > Changes since v2: > - fixed trigger type in DTS > - new explanations in binding documentation > - added support for A31 (sun6i) Ping _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/linux-arm-kernel