booting a PXA250, bad memory setup

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Hi.

Has anyone here had much luck booting a PXA250? Unfortunately I have no 255 to compare with at present, but I cant get this working.

I've been trying to use a modified version of the bootldr memory setup code, however its not well documented, and worse still, the reference to the PXA OS developers guide appears to be out of date, so its impossible to find the original source/inspiration of this code.

Basically, I can get the right values programmed into MDREFR and MDCNFG but the sequencing appears to be wrong. My board does come up, and much stuff does run, but (predicatbly) it crashes left right and center.

surely this cant be too far from working, but I cant for the life of me see why it doesnt.

Heres the guts of my code:

        .macro wait
        ldr     r3,OSCR_BASE
        mov     r1,#0
        str     r1,[r3,#0x10]   @ OSCR
        mov     r1, #0x300 @ 200 usec is x2e1 so this shouldbe fine
1:
        ldr     r2,[r3,#0x10]   @ OSCR
        cmp     r1,r2
        bgt     1b
        .endm

<clock setup> // looks ok...

@ Setup memory - see 6-77 (pg 259) of 278693-001.pdf
        wait  @corrupts r1,r2,r3

        ldr     r0, MEM_BASE

@ Setup the MSCx registers (step 2)

        ldr     r1,MSC0_INIT
        str     r1,[r0,#MSC0_OFFSET] //; spec says to ldr the mscs after
        ldr     r2,[r0,#MSC0_OFFSET]

        ldr     r1,MSC1_INIT
        str     r1,[r0,#MSC1_OFFSET] //; spec says to ldr the mscs after
        ldr     r2,[r0,#MSC1_OFFSET]
        ldr     r1,MSC2_INIT

        str     r1,[r0,#MSC2_OFFSET] //; spec says to ldr the mscs after
        ldr     r2,[r0,#MSC2_OFFSET]

@ Step 5 - SDRAM config
        // MDREFR_STEP_5_INIT ==
        ldr     r1,MDREFR_STEP_5_INIT
        str     r1,[r0,#MDREFR_OFFSET]

@ Step 6 - Synch static memory (not present)
        mov     r1,#0
        str     r1,[r0,#SXCNFG_OFFSET]

@ Step 7 - SDRAM config part 2
        //; MDREFR self refresh turned off
        ldr     r1,[r0,#MDREFR_OFFSET]
        orr     r1,r1,#MDREFR_K1RUN
        orr     r1,r1,#MDREFR_K2RUN
        bic     r1,r1,#MDREFR_SLFRSH
        orr     r1,r1,#MDREFR_E1PIN
//      orr     r1,r1,#MDREFR_APD
        str     r1,[r0,#MDREFR_OFFSET]
        //; MDCONFIG setup up but not enabled
        ldr     r1,MDCNFG_STEP_7_INIT
        str     r1,[r0,#MDCNFG_OFFSET]

@ Step 8:       wait for the sdclocks to stabilize (200 usec)
        wait   @ corrupts r1 r2 r3

// Disable dcache?

@ Step 9 - trigger refresshes by reading sdram
        mov     r0,#0xa0000000
        ldr     r3,=0x200
        mov     r2,#0
20:
        ldr     r1,[r0]
        add     r2,r2,#1
        cmp     r3,r2
        bgt     20b
 // Enable Dcache ?

@ Step 10:      enable the sdram in the mdconfig register
        ldr     r0,MEM_BASE
        ldr     r1,[r0,#MDCNFG_OFFSET]
        orr     r1,r1,#MDCNFG_DE0
//      orr     r1,r1,#MDCNFG_DE1
        str     r1,[r0,#MDCNFG_OFFSET]

@ Step 11   write out the register mode offset value to the sdram
        ldr     r0,MEM_BASE
        mov     r1,#0
        str     r1,[r0,#MDMRS_OFFSET]

MDREFR_STEP_5_INIT:     .long (MDREFR_K0DB2 | MDREFR_K0FREE |
                               MDREFR_SLFRSH | 0x017)
MDCNFG_STEP_7_INIT:     .long 0x000009c8

MSC0_INIT:              .long 0x299CA2D2
MSC1_INIT:              .long 0x124c2989
MSC2_INIT:              .long 0x29840ABC

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