|
|
Re: [PATCH 1/2] ARM: vmlinux.lds.S: do not hardcode cacheline size as 32 bytes |
On 01/16/12 07:44, Will Deacon wrote: > The linker script assumes a cacheline size of 32 bytes when aligning > the .data..cacheline_aligned and .data..percpu sections. > > This patch updates the script to use L1_CACHE_BYTES, which should be set > to 64 on platforms that require it. > > Signed-off-by: Will Deacon <will.deacon@xxxxxxx> > --- > > v2: incorporated suggestions from Stephen Boyd What do you think about aligning the exception fixup table to the same value? -- Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
[Linux ARM (vger)] [Linux ARM MSM] [Linux Omap] [Linux Arm] [Linux Tegra] [Fedora ARM] [eCos] [Linux Fastboot] [Gcc Help] [Git] [DCCP] [IETF Announce] [Security] [PDAs] [Linux] [Linux MIPS] [Yosemite Campsites] [Photos]
|
|